1. Field of the Invention
The present invention relates to a decoder technique applied to channel coding and, more particularly, to a method applied to low density parity check (LDPC) decoder and the operating circuit thereof.
2. Description of Related Art
The function of error correction code (ECC) is to restore corrupted data that has been destroyed due to bad reliability of transmission medium or interference of external factors as far as possible. Low density parity check (LDPC) code has powerful decoding performance close to the Shannon limit, and is a high-efficiency and high-speed channel coding technique. LDPC code will be widely used when data communication speed reaches several GB/s in the future.
In high-speed communication systems, the decoding procedure of LDPC decoder is described below. First, the decoder is initialized. Check nodes and bit nodes are then updated in turn. After update, whether the overlap number in the data sequence exceeds the predetermined maximum overlap number or the decoded bits satisfy the limit of check matrix. If the answer is yes, the whole procedure is terminated, and the decoded bits are outputted; otherwise, the above steps are repeated till the end.
The above LDPC decoder divides the decoding procedure into two phases: the phase of check nodes 10 and the phase of bit nodes 12, as shown in FIG. 1. Usually, the phase of bit nodes 12 starts to sum up after the phase of check nodes 10 is finished, and the decoder needs to store output messages of these two nodes 10 and 12. Therefore, it is necessary for the decoder to have sufficient corresponding check node processor (CNP) sum message memory 14 and bit node processor (BNP) sum message memory 16 to store output messages generated by the check nodes 10 and the bit nodes 12, respectively. Under this premium, an LDPC code with a longer encoding length will result in increased hardware area and complexity, and will also cause greatly reduced decoding efficiency and raised power consumption.
Accordingly, the present invention aims to propose an operating method applied to LDPC decoder and the circuit thereof to effectively the above problems in the prior art.